Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■Memory window
Target Hi-Res
Explanation o In Hi-Res, memory windows can be used in banks 8 and 9 and banks A and B.
Each memory window is 128KB wide, and can project any address in the
CPU's memory space.
o At startup, memory 100000-101FFFFh appears in banks 8 and 9, and memory
102000-103FFFFh appears in banks A and B. Although it is a private function,
Hi-Res machines other than XA also have memory that appears only in the range
80000-BFFFFh. However, machines equipped with 386 have memory that is only
located in the range 80000-BFFFFh. The memory is mapped with OUT 91h, 08h, OUT
93h, and 0Ah.
Related 0000:0481h bit 2
8000:0000-9000:FFFFh
A000:0000-B000:FFFFh
I/O 0091h
Name 08h,09h Bank address specification
Function
[READ] None
[WRITE] RAM window mapping setting
Bits 7-0: Memory address
* Bit 0 is ignored.
Explanation o The upper 8 bits (bits 23-17) of the memory address to be mapped to the physical
address space of 80000-9FFFFh are output to bits 7-1 of this port. The value of bit 0 is ignored.
o At startup, OUT 91h,10h state.
u On PC-98XA, memory will not be mapped if a value less than 10h is output.
u On PC-98XL, hidden memory will only appear when 08h is output.
Even if 0Ah is output, the hidden memory for the 0Ah and 0Bh banks will not appear.
h It is known that hidden memory exists in PC-98XL^2 and later, but it is unknown whether
the hidden memory for the 0Ah and 0Bh banks will not appear in this window.
Related I/O 0093h
I/O 0093h
Name 0Ah,0Bh Bank address specification
Function
[READ] None
[WRITE] RAM window mapping setting
bits 7-0: Memory address
* Bit 0 is ignored.
Explanation o The upper 8 bits (bits 23-17) of the memory address to be mapped to the physical address space
A0000-BFFFFh are output to bits 7-1 of this port. The value of bit 0 is ignored.
o At startup, OUT 93h,12h state.
u On PC-98XA, memory will not be mapped if a value less than 10h is output.
u On PC-98XL, hidden memory will only appear when 0Ah is output. Even if 08h is output, hidden memory for banks 08h, 09h will not appear.
h It is known that hidden memory exists in PC-98XL^2 and later, but it is unknown whether hidden memory
for banks 08h and 09h will not appear in this window.
Related I/O 0091h
-------------------------------------------------------------------------------
■Control port for EMS board
Applicable PC-9801-53
PC-98HA
PC-9801N, NS, NS/E, NC, NS/T, NL, NS/L, NA, NS/R
PC-9801DX, UR, UF
Explanation o The EMS board has four memory windows, each 16KB in size, in the C bank of the memory space, and can project independent memory pages.
o The memory addresses used by hardware EMS are fixed, so in order to use it on a model equipped with a sound BIOS ROM, the ROM must be separated.
Related 0000:0410-0417h■[PC-98HA]
C000:0000-3FFFh
C400:0000-3FFFh
C800:0000-3FFFh
CC00:0000-3FFFh
I/O 08E1h
Name Page frame #0 address setting
Undocumented
Function
[READ] None
[WRITE]
bit 7-0: C000h SEL BANK
Explanation o Specifies the page address of the memory to be projected to EMS page frame 0
Related I/O 08E9h
I/O 08F0h,08F2h - 0008h bit 7-0
C000:0000-3FFFh
I/O 08E3h
Name Page frame #1 address setting
Undocumented
Function
[READ] None
[WRITE]
bit 7-0: C400h SEL BANK
Explanation o Specifies the page address of the memory to be projected to EMS page frame 1
Related I/O 08E9h
I/O 08F0h,08F2h - 0009h bit 7-0
C400:0000-3FFFh
I/O 08E5h
Name Page frame #2 address setting
Undocumented
Function
[READ] None
[WRITE]
bit 7-0: C800h SEL BANK
Explanation o Specifies the page address of the memory to be projected to EMS page frame 2
Related I/O 08E9h
I/O 08F0h,08F2h - 000Ah bit 7-0
C800:0000-3FFFh
I/O 08E7h
Name Page frame #3 address setting
Undocumented
Function
[READ] None
[WRITE]
Bit 7-0: CC00h SEL BANK
Explanation o Specifies the page address of the memory to be projected to EMS page frame 3
Related I/O 08E9h
I/O 08F0h,08F2h - 000Bh Bit 7-0
CC00:0000-3FFFh
I/O 08E9h
Name Protected memory address setting
Undocumented
Function
[READ] None
[WRITE]
Bit 7-0: Memory address (A23-A20)
Explanation o Sets the memory address when using the EMS board as protected memory.
Related I/O 0567h
I/O 08E1h
I/O 08E3h
I/O 08E5h
I/O 08E7h
I/O 08F0h,08F2h - 0006h bit 15-8
I/O 08F0h,08F2h - 0008h bit 15-8
I/O 08F0h,08F2h - 0009h bit 15-8
I/O 08F0h,08F2h - 000Ah bit 15-8
I/O 08F0h,08F2h - 000Bh bit 15-8
-------------------------------------------------------------------------------
■16MB space memory control
Explanation o On models that can add memory above 16MB, you can choose whether to use the 1MB area from
F00000 to FFFFFFh as system or normal RAM. This space is called the 16MB system space.
o On machines with extended graphic architecture, the 16MB system space may be used as a packed
pixel VRAM buffer in 256-color mode, or as a VRAM window for a window accelerator board.
In this case, this space must be used as the 16MB system space.
o When the 16MB system space is set to [Separate] in the System Setup menu, this space can be
used in the same way as other RAM spaces.
o On models with PCI bus or RED WOOD, the setting to enable the use of the 16MB system space
cannot be enabled unless the same setting is made to the chipset in addition to this I/O.
Related F00000 to FFFFFFh
I/O 043Bh
Name 16MB space memory control
Undocumented
Target PC-9821Af, Ap2, As2, Bp, Bs, Be, Bf, Cs2, Ce2, Ts, An, Xt, Xa, Xn, Xp, Xs, Xe
PC-9821Np, Ns, Ne2, Nd, Es
PC-9801BA2, BS2, BX2, BA3, BX3, BX4, NL/A, NS/A
Function
[READ/WRITE]
bit 7-3: Unused (always 00000b)
bit 2: 16MB space control
1 = Normal memory space
0 = Used by system
bit 1,0: Unknown (always 00b)
Explanation o Sets whether the memory space from F00000 to FFFFFFh is used by the system or as normal memory space.
o If the 16MB space is used as normal memory, the extended graphics VRAM at F00000-F7FFFFh cannot be used.
However, even in this case, the extended graphics VRAM can be used by using addresses FFF00000-FFF7FFFFh.
o For models with PCI bus, in addition to this I/O, settings must also be made for PCMC, PCI-C bus bridge,
and PCI-local bus bridge.
Related I/O 881Eh bit 0■[98NOTE,98FiNE]
I/O 8F1Eh bit 0■[Other than 98NOTE,98FiNE]
------------------------------------------------------------------------
■SIMM socket status
Target PC-9801-61 type SIMM equipped models
Explanation o For PC-9801-61 type SIMM equipped models, each SIMM socket is decoded with a fixed address, so SIMMs must be added in ascending order of
SIMM socket number. ITF uses this SIMM socket status to check which SIMM socket has a SIMM installed.
I/O 043Bh
Name SIMM socket status
Undocumented
Function
[READ/WRITE]
bit 7-0: SIMM socket #7-#0 status
1 = SIMM installed
0 = SIMM not installed
Explanation o Obtains whether a PC-9801-61 type SIMM is installed in each socket.
u For models that can be equipped with 16MB or more of memory, this I/O port is used for another purpose, so caution is required.
Related
===============================================================================
■BIOS/ITF bank switching
Target ITF-equipped devices
Explanation o In normal mode, banks 8 and 9 can be separated for use with I/O bank memory installed in the expansion slot. Normally, this is set with dip
switches 3-6, but it can also be set by software.
o In normal mode, banks 8 and 9 can also be used as RAM windows. Any address up to 16MB can be projected.
o As frame memory for EMS (Expanded Memory Specification), bank B can be used.
On EMS-equipped devices, 64KB of memory can be made to appear in bank B. This area is usually used as VRAM.
u As a rule, the state of these bank switches cannot be read. Some devices can read these,
but the method varies from device to device and is not compatible.
Related 0000:0481h bit 5,4
B000:0000-FFFFh
F800:0000-7FFFh
I/O 08F0h,08F2h - 0006h bit 0
I/O A46Eh bit 7
I/O 043Dh
Name Cache status ■ [Machines with 486 or higher CPU]
BIOS/ITF bank switching
Undocumented
Function
[READ]
bit 7-3: Unknown
bit 2: Cache status
1 = The previous read operation hit the cache
0 = The previous read operation missed the cache
bit 1,0: Unknown
* It is possible to check whether the previous read operation of the CPU was a cache hit.
[WRITE]
bits 7-0: BIOS/ITF bank switch
---------------------------------------------------------------
00000000b(00h): ITF ROM selection ■ [Hi-Res]
---------------------------------------------------------------
00000010b(02h): Unknown
---------------------------------------------------------------
00010000b(10h): ITF ROM selection ■ [Normal]
MENU ROM selection ■ [H98S]
---------------------------------------------------------------
00010010b(12h): BIOS ROM selection
---------------------------------------------------------------
00011000b(18h): ITF ROM selection ■ [H98S]
---------------------------------------------------------------
* If ITF ROM is selected, F8000-FFFFFh will be switched to ITF ROM.
When switching to ITF ROM, the state of E8000-F7FFFh is undefined.
* ITF ROM is selected at reset. BIOS is selected at disk boot.
* On machines with a 486 or higher CPU, caching is disabled for ITF when ITF is selected. Caching is enabled for BIOS when BIOS is selected.
Explanation o Sets the memory contents of the space from F8000 to FFFFFh where the BIOS ROM is located.
u On machines with a 486 or higher CPU, the FLUSH# signal becomes active when WRITE is performed.
Related I/O 043Fh
F800:0000-7FFFh
I/O 043Fh
Name Various bank switching
Undocumented
Function
[READ] None
[WRITE]
Bits 7-0: Various bank switching
---------------------------------------------------------------
001000n0b: VRAM/EMS bank switching
0(20h) = VRAM
1(22h) = EMS
* Used when switching between page frame and VRAM in NEC EMS (page frame
starts at B0000h, and VRAM and bank switching is performed).
* VRAM is selected at reset.
Related 0000:0480h bit 5,4
B000:0000-FFFFh
I/O 08F0h,08F2h - 0006h bit 0
I/O A46Eh bit 7
---------------------------------------------------------------
010000n0b: Unknown■[RA21 research]
1(42h) = 386-20MHz
0(40h) = 386-16MHz
* In the RA21 ITF ROM, when the 386 CPU is running, n=0 is output when the
clock frequency is 16MHz, and n=1 when the clock frequency is 20MHz.
---------------------------------------------------------------
100000n0b: 08h,09h bank control
0(80h) = Internal RAM selection
1(82h) = Expansion slot selection
* For I/O bank type memory boards, controls whether or not the 08h,09h banks
can access the memory on the expansion slots.
* When the internal RAM is selected, the memory on the expansion slots cannot
be accessed from the 08h,09h banks.
* When the expansion slot is selected and an area in the range of 00000-9FFFFh
is mapped to the RAM window, if an area where no RAM exists is mapped or if
BIOS RAM is mapped and BIOS RAM access is disabled, the internal RAM is
disconnected and the memory on the expansion slots can be accessed.
* When reset, the internal RAM is selected.
* When the internal RAM is selected during 386 CPU operation, the memory on
the expansion slots between 80000-9FFFFh is not accessed.
* When the internal RAM is selected during V30 CPU operation, the memory in
the expansion slot from 80000 to 9FFFFh will not be accessed unless the
microswitch in the expansion slot is pressed. However, if the microswitch is
pressed, when the CPU accesses the 08h and 09h banks, the memory in the
expansion slot will also be accessed, so care must be taken.
* On the PC-9801RA2, the control is not reflected until the next OUT 0461h is
executed. No matter what area is assigned to the RAM window, selecting an
expansion slot will access the memory in the expansion slot.
Related I/O 0461h
I/O 0463h
I/O 08F0h,08F2h - 0006h bit 4
---------------------------------------------------------------
110000n0b: Internal SASI BIOS RAM/ROM selection
0(C0h) = ROM active
1(C2h) = RAM active
* Valid when the internal 27 HD BIOS is enabled on port 053Dh. However, the
internal ROM must not be active if memory in the range of D7000-D7FFFh is
present in the expansion slot.
---------------------------------------------------------------
11000n00b: Internal SCSI BIOS RAM/ROM selection
0(C0h) = ROM active
1(C4h) = RAM active
---------------------------------------------------------------
10100000b: Cache flush
---------------------------------------------------------------
11100nnnb: ROM bank specification
000b =
001b =
010b =
011b =
100b =
101b =
110b =
111b =
* Directly specifies the bank address of the ROM that appears in the
F800:0000-7FFFh area. Used for rewriting flash ROM, etc.
* Valid on PC-9821Af and later models.
----------------------------------------------------------------
Explanation o Switches between various memory banks.
o On machines with a 486 or higher CPU, the FLUSH# signal becomes active during WRITE.
u The PC-9801FA cannot use the INVD and WBINVD instructions. Therefore, to flush the cache, OUT 043Fh, A0h must be executed.
This function is supported not only by the PC-9801FA, but also by other models.
Related I/O 043Dh
I/O 0461h
Name RAM window mapping setting
Undocumented
Target Normal
Function
[READ] None
* However, there are models that can read, such as PC-9821Xe10 and PC-9801BX4.
[WRITE] RAM window mapping setting
Bits 7-0: Memory address
* Bit 0 is ignored.
Explanation o Specifies the address of the memory to be mapped to the RAM window (banks 08h and 09h). Internal RAM from address 80000h onwards can be
specified in units of 20000h bytes (128KB). The upper 8 bits of the address (bits 23-17) are output to bits 7-1 of this port.
The value of bit 0 is ignored.
o For the operation when non-existent memory is mapped, see the "8-9 bank control" section of I/O 043Fh.
u Memory of 1MB or more can be mapped and accessed even when the V30 CPU is running.
When accessing memory of 1MB or more via the RAM window, the mask state of A20 is not affected.
u Unlike the RAM window in high-resolution mode, the RAM window position also has its own physical memory.
u If an internal RAM other than 80000-9FFFFh is mapped to the RAM window, the access speed will be slower than when 80000-9FFFFh is mapped.
o At reset, 80000-9FFFFh is selected.
u On machines with a 486 or later CPU, the FLUSH# signal becomes active when WRITE is performed.
Related I/O 043Fh - 80h,82h
I/O 0463h
I/O 0463h
Name RAM window mapping setting
Undocumented
Target Normal
Function
[READ] None
* However, there are models that can read, such as PC-9821Xe10 and PC-9801BX4.
[WRITE] RAM window mapping setting
Bits 7-0: Memory address
* Bit 0 is ignored.
Explanation o Specifies the address of the memory to be mapped to the RAM window (0Ah, 0Bh bank). Internal RAM from address 80000h onwards can be
specified in units of 20000h bytes (128KB). The upper 8 bits of the address (bits 23-17) are output to bits 7-1 of this port.
The value of bit 0 is ignored.
u Under normal conditions, the memory space mapped to this area cannot be accessed.
o At reset, A0000-BFFFFh is selected.
On machines with a 486 or later CPU, the FLUSH# signal becomes active when WRITE is performed.
Related I/O 043Fh - 80h,82h
I/O 0461h
I/O 053Dh
Name Memory enable control
Undocumented
Target 386 or higher CPU equipped machines ■ [PCI equipped models, RED WOOD equipped models excluded]
Function
[READ] None
[WRITE] Memory enable control
bit 7: Sound BIOS
1 = Enable
0 = Disable
bit 6: HD-BIOS enable control for SASI built-in HDD
1 = Enable
0 = Disable
* Controls whether the built-in HD-BIOS appears in the space from D7000 to D7FFFh.
* The access speed of this ROM is the same as the ROM installed in the expansion slot.
* Even if the ROM is enabled, the MRC/MWC/A19 signal is output to the expansion slot. Disabled at reset.
bit 5: HD-BIOS enable control for SCSI internal HDD
1 = Enable
0 = Disable
bit 4: HD-BIOS enable control for IDE internal HDD
1 = Enable
0 = Disable
bit 3: Unused
bit 2: BIOS RAM access enable control
1 = Disable
0 = Enable
* Functions for E0000-FFFFH in RA2, and for C0000-FFFFH in RA21.
* Controls whether to allow access when the address is mapped to the RAM window.
* If the access is not enabled, the address cannot be read or written from the RAM window.
* Access is enabled at reset. Disabled in boot state.
bit 1: BIOS RAM/ROM SELECT
1 = BIOS RAM selection
0 = BIOS ROM selection
* Selects whether RAM or ROM will appear in the BIOS area from E8000-FFFFFh.
* BIOS ROM is selected at reset. After transferring the contents of the BIOS
ROM to the BIOS RAM, the BIOS RAM is selected.
bit 0: Unused
Explanation o This port cannot be read, so even if you want to change only one bit, you must write while considering the state of the other bits.
Related I/O 00F0h bit 5
-------------------------------------------------------------------------------
■SIMM controller
Applicable PC-9821Af, Ap2, As2, Bp, Bs, Be, Bf, Ts, Cs2, Ce2, An, Xn, Xp, Xs, Xe, Cb, Cx, Cb2, Xe10
PC-9801BA2, BS2, BX2, BA3, BX3, BX4
Explanation o Machines after the PC-9821Af use JEDEC-spec SIMMs. In machines with a PCI bus, SIMMs are controlled by PCMC,
but in machines without a PCI bus, SIMMs are controlled by the 98's own SIMM controller.
o To set the base address of each SIMM slot, a decode range is specified for each slot.
I/O 0530h
Name SIMM socket address
Undocumented
Function
[READ/WRITE]
bit 7: Address specification
1 = Specify limit address
0 = Specify base address
bit 6-4: Unused (always set to 000b)
bit 3-0: SIMM socket number
0000b = For HDD model built-in memory
0001b = Unused
0010b = Socket #1 RAS0,RAS2 range specification
0011b = Socket #1 RAS1,RAS3 range specification
0100b = Socket #2 RAS0,RAS2 range specification
0101b = Socket #2 RAS1,RAS3 range specification
0110b = Socket #3 RAS0,RAS2 range specification
0111b = Socket #3 RAS1,RAS3 range specification
1000b = Socket #0 RAS0,RAS2 range specification
1001b = Socket #0 RAS1,RAS3 range specification
1010b = Unavailable
:
1111b = Unavailable
Explanation o Specifies the range of memory space for outputting chip select for SIMMs installed in each socket.
Related I/O 0531h
I/O 0531h
Name SIMM address specification
Undocumented
Function
[READ/WRITE]
Bit 7-0: Address setting
* I/O 0530h When bit 7 is 1, it specifies the limit address, and when it is 0, it specifies the base address.
■[When specifying base address]
Specifies bits 27-20 of the base address.
■[When specifying limit address]
Specifies bits 27-20 of the base address. In this case, the value of bits 19-0 all set to 1 becomes the base address.
Explanation o Specifies the range of memory space for outputting chip select for SIMMs installed in each socket.
Related I/O 0530h
-------------------------------------------------------------------------------
■Other memory management
Explanation o Some models have their own memory management functions. However, since there is often no compatibility between models, care must be taken when
operating these. In addition, it is best to avoid operating them as much as possible.
I/O 0567h
Name Protected memory registration
Undocumented
Target Models with 286 or higher CPUs■[Excluding models with 16MB or more memory]
Function
[READ/WRITE]
bit 7-0: Maximum protected memory
Explanation o Sets the maximum address of the installed protected memory in 128KB units.
o Details unknown.
Related
I/O 063Ch
Name Memory bank switching
Undocumented
Target PC-9821Xt, Xf, Xa, Xn, Xp, Xs, Xe, Cf, Cb, Cx, Xa16, Xa13, Xa12, Xa10, Xa9, Xa7, Xa7e, Xe10, Xa16, Xt13, Xb10, Xv13, Cx2, Cb2, Cx3, Cb3, V10, V7
PC-9801BA3, BX3, BX4
Function
[READ/WRITE]
Bits 7-2: Unused
Bits 1,0: BIOS ROM bank
11b = Configuration routines for C bus PnP boards, etc.
10b = PCI BIOS, PnP BIOS, etc.
01b = IDE BIOS (normal)
00b = Unknown
Explanation o Sets the ROM bank for the memory space D8000 to DFFFFh.
Related D800:0000 to D800:1FFFh (IDE)
D800:0000 to D800:3FFFh
I/O 063Dh
Name Various memory status acquisition
Undocumented
Target PC-9821Af･Ap2･As2･Bp･Bs･Be･Bf･Cs2･Ce2･Ts･An･Xn･Xp･Xs･Xe
PC-9801BA2･BS2･BX2･BA3･BX3･BX4
[READ]
bit 7,6: 2ND CACHE RAM board setting
■[PC-9821Ap2･As2･BA2･Bp･Xn･Xp･Xs･Ap3･As3]
00b = 2 2ND CACHE RAM BOARDs
01b = 2ND CACHE BOARD ERROR
10b = 1 2ND CACHE RAM BOARD
11b = No 2ND CACHE RAM
bit 5: Low mode flag ■ [PC-9821As2/Ce2]
1 = Low mode
0 = High/Middle mode
Bits 4-2: Unknown
Bit 1: IDE ROM address in high-resolution mode
■ [PC-9821Af/Ap2/As2/An/Ap3/As3]
0 = E6000-E7FFFh is ROM, E8000-E9FFFh is RAM
1 = E8000-E9FFFh is ROM, EA000-EBFFFh is RAM
Bit 0: Unknown
Explanation u Gets the number of second caches
u Gets the IDE BIOS ROM address in high-resolution mode. Changes depending on whether or not a line adapter is used in the system setup menu.
I/O 063Eh
Name Flash ROM power supply voltage control
Undocumented
Target PC-9821An, Xt, Xa, Xf, Xn, Xp, Xs, Xe, Cf, Cx, Cb, Ap3, As3, Xa16, Xa13, Xa12, Xa10
Xa9, Xa7, Xa7e, Xt16, Xt13, St15, Xv13, Xb10, Xe10, Np, Ns, Es, Ne2, Nd, Ld, Lt, Nf, Nm
Ne3, Nd2, Na12, Na9, Na7, Nb7, Nx, Lt2
PC-9801NL/A, BA3, BX3, BX4
Function
[READ/WRITE]
bit 7-2: Unknown
bit 1: Unknown ■ [PC-9821Xe10, PC-9801BX4]
bit 0: Flash ROM power supply voltage
1 = +12V
0 = +5V
Explanation u When updating the flash ROM, this is used to set the power supply voltage given to the ROM to +12V.
u Do not operate carelessly as this may cause a fatal failure.
Related I/O 043Fh - E0 to EEh
I/O 063Fh
Name Cache related
Undocumented
Target PC-9821An, Xn, Xp, Xs, Xe, Cx, Cb, Xe10
PC-9801BA3, BX3, BX4
Function
[READ/WRITE]
bit 7: CPU internal cache control
1 = WriteBack
0 = WriteThrough
* Only valid when the CPU is a Pentium processor, WriteBack Enhanced DX2, or PentiumODP
bit 6: Unknown
bit 5: CPU internal cache control
1 = Enabled
0 = Disabled
bit 4: Second cache control
1 = Enabled
0 = Disabled
bit 3-1: Unused
bit 0: Unknown
Explanation u Controls the CPU internal cache and second cache.
u Do not operate carelessly as it may cause a fatal error.
o Details unknown
Related I/O 043Fh
I/O 063Dh
I/O 9896h
Name CPU cache control
Undocumented
Target PC-H98
Function
[WRITE]
Bit 7-0: CPU cache control
00h= Secondary cache ON
04h= Secondary cache OFF
Explanation o Turns the CPU secondary cache ON/OFF.
Related